[VHDL] 状态机的运行

光之山川 发布于 2017/12/10 20:21
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问题背景:在Quartus2 9.0版本下进行指令分析和执行系统的设计

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Reg_and_control is
port(clk,clk1:in std_logic;
--clk:pin_A14,clk1--signal to control states machine
     ctrl:in std_logic;--ctrl=1:input data,ctrl=0:run the states machine
     Reset:in std_logic; --Reset=0:state=st0
     PC_Wr:in std_logic; --PC read enable
     data:in std_logic_vector(7 downto 0);
     Ri:out std_logic_vector(31 downto 0);
     PC_out:out std_logic_vector(7 downto 0);
     output:out std_logic_vector(2 downto 0));
end entity;

architecture one of Reg_and_control is
shared variable R0,R1,R2,R3,PC:std_logic_vector(7 downto 0);
type states is(st0,st1,st2,st3,st4,st5);
signal current_state:states:=st0;
signal next_state:states;

begin

process(clk1)--States Machine's clk
begin
if Reset='0' then
   current_state<=st0;
else
if clk1'event and clk1='1' then
   current_state<=next_state;
end if;
end if;
end process;

process(current_state,ctrl)
begin
if ctrl='1' then
   if clk'event and clk='1' then
      if PC_Wr='1' then
         PC:=data;
      else
         PC:=PC;
      end if;
   end if;
else
case current_state is
 when st0 =>
      output<="010";
      next_state<=st1;
      R0:="00000001";R1:="00000001";R2:="00000001";R3:="00000001";
      PC:=PC+1;
 when st1 =>
      output<="011";
      next_state<=st2;
      R0:="00000011";R1:="00000011";R2:="00000011";R3:="00000011";
      PC:=PC+1;
 when st2 =>
      output<="100";
      next_state<=st3;
      R0:="00000111";R1:="00000111";R2:="00000111";R3:="00000111";
      PC:=PC+1;
 when st3 =>
      output<="101";
      next_state<=st4;
      R0:="00001111";R1:="00001111";R2:="00001111";R3:="00001111";
      PC:=PC+1;
 when st4 =>
      output<="110";
      next_state<=st5;
      R0:="00011111";R1:="00011111";R2:="00011111";R3:="00011111";
      PC:=PC+1;
 when st5 =>
      output<="111";
      next_state<=st0;
      R0:="00111111";R1:="00111111";R2:="00111111";R3:="00111111";
      PC:=PC+1;
  when others=>NULL;
 end case;
 end if;
 Ri<=R0&R1&R2&R3;
 PC_out<=PC;
end process;

end architecture;

功能:在ctrl=1时对PC进行置数,即把data的值赋给PC,在ctrl=0时运行状态机。

问题:在ctrl从1变成0时,状态机不会立刻变成st0,而是在Reset的低电平处才被复位到0

同时当ctrl从1变成0时,PC的值不会自加

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状态机是干嘛的?

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回复@开源中国首席卡牌中单 : 状态机是用来模拟计算机CPU里面指令执行的步骤的
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