Verilog低通滤波器输出数据问题

小小小娇 发布于 2015/09/03 09:07
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如下代码:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/08/27 11:05:50
// Design Name: Zhao Yuejiao
// Module Name: lowpassfliter
// Project Name: Lpwpassfliter
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////////
module lowpass_fliter(out,in,clk,rst);
parameter size_in = 16;
parameter size_out = 2*size_in+1;

integer h0 = 8'sd1;
integer h1 = 8'sh4;
integer h2 = 8'sh8;
integer h3 = 8'sd11;
integer h4 = 8'sd12;
integer h5 = 8'sd11;
integer h6 = 8'sd8;
integer h7 = 8'sd4;
integer h8 = 8'sd1;

 
//integer h9 = 8'd11;
//integer h10 = 8'd8;
//integer h11 = 8'd4;
//integer h12 = 8'd1;
//integer h13 = 8'd0;
//integer h14 = 8'hff;
//integer h15 = 8'hff;
//integer h16 = 8'd0;
 
    output signed [size_out-1:0] out;
    input signed [size_in-1:0] in;
    input clk,rst;
    
   
  
    reg signed [size_in-1:0] samples1;
    reg signed [size_in-1:0] samples2;
    reg signed [size_in-1:0] samples3;
    reg signed [size_in-1:0] samples4;
    reg signed [size_in-1:0] samples5;
    reg signed [size_in-1:0] samples6;
    reg signed [size_in-1:0] samples7;
    reg signed [size_in-1:0] samples8;
//     reg [size_in-1:0] samples9;
//       reg [size_in-1:0] samples10;
//       reg [size_in-1:0] samples11;
//       reg [size_in-1:0] samples12;
//       reg [size_in-1:0] samples13;
//       reg [size_in-1:0] samples14;
//       reg [size_in-1:0] samples15;
//       reg [size_in-1:0] samples16;
    assign out = h0*in+h1*samples1+h2*samples2+h3*samples3+h4*samples4+h5*samples5+h6*samples6+h7*samples7+h8*samples8;//+h9*samples9+h10*samples10+h11*samples11+h12*samples12+h13*samples13+h14*samples14+h15*samples15+h16*samples16;
         initial
       begin
     
         samples1<=0;
         samples2<=0;
         samples3<=0;
         samples4<=0;
         samples5<=0;
         samples6<=0;
         samples7<=0;
         samples8<=0;
        end
     always@ (posedge clk or negedge rst)
    if(rst==1)
    begin //初始化
  
    samples1<=0;
    samples2<=0;
    samples3<=0;
    samples4<=0;
    samples5<=0;
    samples6<=0;
    samples7<=0;
    samples8<=0;
    end
    else
    begin

    samples1<=in;
    samples2<=samples1;
    samples3<=samples2;
    samples4<=samples3;
    samples5<=samples4;
    samples6<=samples5;
    samples7<=samples6;
    samples8<=samples7 ;
    
    end  //匹配else
    endmodule

testbench如下:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/08/27 11:45:40
// Design Name:
// Module Name: test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module test;
 reg clk,rst ;
 reg [15:0] in;
 wire [31:0] out;
 lowpass_fliter exm(.clk(clk),.out(out),.in(in),.rst(rst) );
 always //给出时钟周期
 begin
 # 20 clk = 0;
 # 20 clk = 1;
 end
 
 reg [15:0] rx_mem[0:326];
 integer cnt= 3'b000;
 integer fp;
     integer j=0;
 //$readmemh("datain.txt",rx_mem);

 initial
 begin
 #40;
 #40 rst = 0;
 #40 rst = 1;
 #40 rst = 0;
  $readmemh("E:\datain.txt",rx_mem);
   fp=$fopen("E:\dataout_verilog2.txt","a"); 
   $monitor(fp,"%d\t",out);
  in = 0;
  rst = 0;  //输入数据
 
     for(integer i=0;i<327;i=i+1)
     begin
     # 40 in = rx_mem[i];
      
           j = j +1;
           if(j%10==0)
           $fwrite(fp,"\n");
        // $display("%d,\t%d,\t%d,\t%d,\t%d");
    end 
 
 end
endmodule

激励数据从文件读入为-17 27 -15 7 18 -25 -134 -484 -1159 582 1949 769 797 -236 679 268 -1865 788 -1417 -69 893 371 -201 195 -496 23 -89 -821 -775 -115 -1085 113 -35 -814 236 102 -101 601 -140 -135 -175 -95 -374 196 -237 0 377 -32 -20 773 350 487 63 -446 166 -296 -450 87 -128 201 426 216 -66 68 -147 46 81 -274 -42 64 -29 387 188 20 209 22 27 -90 -157 -106 187 188 77 84 -137 -12 -672 -865 1045 1606 586 665 -563 1332 -702 -828 503 -1250 337 455 133 -411 109 -490 142 56 -878 -336 -438 -1015 293 -538 -530 185 23 115 329 -81 -279 119 -147 -55 132 -292 -6 258 -193 16 760 559 412 -47 -358 304 -340 -357 109 -265 189 338 59 -150 206 -2 226 -27 -288 -58 -9 -35 445 98 76 129 89 23 -30 -48 -11 -46 59 201 97 -190 17 -55 -1128 410 1619 820 379 -554 974 57 -872 578 -745 -50 240 167 -568 -178 -195 -30 380 -828 -318 -463 -919 72 -349 -463 -53 -25 -12 151 -61 -215 193 71 60 171 -390 30 58 32 -69 4 1098 529 30 -416 -179 823 -847 363 -361 -232 218 166 2 -27 256 19 323 -246 -390 169 -151 339 419 -252 102 53 202 128 -9 -235 79 266 -22 -74 -28 42 390 -561但是滤波器的输出数据为-85 -1 -46 8 118 77.。。。按照逻辑第一个数据不是应该为-17吗?请大神指点一下?不胜感激~

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